Nickel-Silicide Contact Technology With Dual Near-Band-Edge Barrier Heights and Integration in CMOS FinFETs With Single Mask

• Published in: IEEE electron device letters Vol. 31; no. 9; pp. 918 - 920
• Main Authors: Sinha, M, Eng Fong Chor, Yee-Chia Yeo
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.09.2010; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Aluminum (Al) implant; Barriers; Charge carrier processes; CMOS; CMOS technology; Contact; Contact resistance; Devices; double-species implant; FinFETs; Germanium silicon alloys; Implants; Nickel; nickel silicide (NiSi); Schottky barrier height; Schottky barriers; Silicides; Silicon germanium; Simplification; Sulfur; sulfur (S) implant; Tuning
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2010.2052586

This letter reports the demonstration of a nickel-silicide contact technology that achieves dual near-band-edge barrier heights (i.e., a low electron barrier height Φ Bn for n-FETs and a low hole barrier height Φ Bp for p-FETs) using just one additional masking and two ion-implant steps. Independent and effective tuning of contact resistance RC is achieved in both p- and n-FinFETs. The compensation effect of aluminum and sulfur implants is studied for the first time and exploited for process simplification. A novel cost-effective integration scheme is shown to give significant I DSAT enhancement for p- and n-FinFETs.