ATCA Control System Hardware for the Plasma Vertical Stabilization in the JET Tokamak

• Published in: IEEE transactions on nuclear science Vol. 57; no. 2; pp. 583 - 588
• Main Authors: Batista, Antonio Joaquim Nunes, Neto, Andre, Correia, Miguel, Fernandes, Ana Maria, Carvalho, Bernardo B, Fortunato, Joao Carlos, Sousa, Jorge, Varandas, Carlos, Sartori, Filippo, Jennison, Mike
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.04.2010; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Amplifiers; ATCA; Channels; Communication system control; Control algorithms; Control boards; Control systems; Control theory; Field programmable gate arrays; Galvanizing; Hardware; Links; Optical amplifiers; Plasma; Plasmas; Processors; Product introduction; real time systems; Signal processing algorithms; Stabilization; Telecommunication control; Tokamaks
• ISSN: 0018-9499; 1558-1578
• DOI: 10.1109/TNS.2010.2042068

A multi-input-multi-output controller for the plasma vertical stabilization was implemented and installed on the Joint European Torus tokamak. The system can attain a control-cycle time of approximately 30 ¿s using ×86 multi-core processors but targets 10 ¿s via Field Programmable Gate Array (FPGA) based processing. The hardware, complying with the Advanced Telecommunications Computing Architecture (ATCA) standard, was in-house designed and implemented to achieve the required performance and consists of: A total of 6 synchronized ATCA control boards, each one with 32 analog input channels which provide up to 192 galvanically-isolated channels, used mainly for magnetic measurements. Each board contains an FPGA, which performs digital signal processing and includes a PCI Express communications interface; An ATCA rear transition module, which comprises up to 8 galvanically-isolated analog output channels to control the fast radial field amplifier (±10 kV, ±2.5 kA). An optical link to digitally control the enhanced radial field amplifier (±12 kV, ±5 kA). Up to 8 EIA-485 digital inputs for timing and monitoring information; An ATCA processor blade with a quad-core processor, where the control algorithm is presently running, connected to the 6 ATCA control boards through the PCI Express interface. All FPGAs are interconnected by low-latency links via the ATCA full-mesh backplane, allowing all channel data to be available on each FPGA running an upcoming distributed control algorithm.