Radio-Frequency Characteristics of Partial Dielectric Removal HR-SOI and TR-SOI Substrates

• Published in: Chinese physics letters Vol. 34; no. 6; pp. 107 - 111
• Main Author: 程实 常永伟 高楠 董业民 费璐 魏星 王曦
• Format: Journal Article
• Language: English
• Published: Chinese Physical Society and IOP Publishing Ltd 01.06.2017
• Subjects: SOI衬底; 共面波导; 射频性能; 射频集成电路; 无线电; 绝缘结构; 金属氧化物半导体; 频率特性
• ISSN: 0256-307X; 1741-3540
• DOI: 10.1088/0256-307X/34/6/068101

High-resistivity silicon-on-insulator （HR-SOI） and trap-rich high-resistivity silicon-on-insulator （TR-S01） sub- strates have been widely adopted for high-performance rf integrated circuits. Radio-frequency loss and non- linearity characteristics are measured from coplanar waveguide （CPW） t lines fabricated on HR-SOI and TR-SOI substrates. The patterned insulator structure is introduced to reduce loss and non-linearity char- acteristics. A metal-oxide-semiconductor （MOS） CPW circuit model is established to expound the mechanism of reducing the parasitic surface conductance （PSC） effect by combining the semiconductor characteristic anal- ysis （pseudo-MOS and C-V test）. The rf performance of the CPW transmission lines under dc bias supply is also compared. The TR-SOI substrate with the patterned oxide structure sample has the minimum rf loss （〈0.2 dB/mm up to 10 GHz）, the best non-linearity performance, and reductions of 4 dB and 10 dB are compared with the state-of-the-art TR-SOI sample＇s, HD2 and HD3, respectively. It shows the potential application for integrating the two schemes to further suppress the PSC effect.