MATRIX16: A 16-Channel Low-Power TDC ASIC with 8 ps Time Resolution

This paper presents a highly configurable 16-channel TDC ASIC designed in a commercial 180 nm technology with the following features: time-of-flight and time-over-threshold measurements, 8.6 ps LSB, 7.7 ps jitter, 5.6 ps linearity error, up to 5 MHz of sustained input rate per channel, 9.1 mW of pow...

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Bibliographic Details
Published inElectronics (Basel) Vol. 10; no. 15; p. 1816
Main Authors Mauricio, Joan, Freixas, Lluís, Sanuy, Andreu, Gómez, Sergio, Manera, Rafel, Marín, Jesús, Pérez, Jose M., Picatoste, Eduardo, Rato, Pedro, Sánchez, David, Sanmukh, Anand, Vela, Oscar, Gascon, David
Format Journal Article
LanguageEnglish
Published Basel MDPI AG 01.08.2021
Subjects
Circuits
Digitization
Interpolation
Power consumption
Time measurement
Vibration
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Summary:This paper presents a highly configurable 16-channel TDC ASIC designed in a commercial 180 nm technology with the following features: time-of-flight and time-over-threshold measurements, 8.6 ps LSB, 7.7 ps jitter, 5.6 ps linearity error, up to 5 MHz of sustained input rate per channel, 9.1 mW of power consumption per channel, and an area of 4.57 mm2. The main contributions of this work are the novel design of the clock interpolation circuitry based on a resistive interpolation mesh circuit and the capability to operate at different supply voltages and operating frequencies, thus providing a compromise between TDC resolution and power consumption.
ISSN:2079-9292
2079-9292
DOI:10.3390/electronics10151816