Testability Evaluation in Time-Variant Circuits: A New Graphical Method
DC–DC converter fault diagnosis, executed via neural networks built by exploiting the information deriving from testability analysis, is the subject of this paper. The networks under consideration are complex valued neural networks (CVNNs), whose fundamental feature is the proper treatment of the ph...
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Published in | Electronics (Basel) Vol. 11; no. 10; p. 1589 |
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Main Authors | , , , , |
Format | Journal Article |
Language | English |
Published |
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01.05.2022
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ISSN | 2079-9292 2079-9292 |
DOI | 10.3390/electronics11101589 |
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Abstract | DC–DC converter fault diagnosis, executed via neural networks built by exploiting the information deriving from testability analysis, is the subject of this paper. The networks under consideration are complex valued neural networks (CVNNs), whose fundamental feature is the proper treatment of the phase and the information contained in it. In particular, a multilayer neural network based on multi-valued neurons (MLMVN) is considered. In order to effectively design the network, testability analysis is exploited. Two possible ways for executing this analysis on DC–DC converters are proposed, taking into account the single-fault hypothesis. The theoretical foundations and some applicative examples are presented. Computer programs, based on symbolic analysis techniques, are used for both the testability analysis and the neural network training phase. The obtained results are very satisfactory and demonstrate the optimal performances of the method. |
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AbstractList | DC–DC converter fault diagnosis, executed via neural networks built by exploiting the information deriving from testability analysis, is the subject of this paper. The networks under consideration are complex valued neural networks (CVNNs), whose fundamental feature is the proper treatment of the phase and the information contained in it. In particular, a multilayer neural network based on multi-valued neurons (MLMVN) is considered. In order to effectively design the network, testability analysis is exploited. Two possible ways for executing this analysis on DC–DC converters are proposed, taking into account the single-fault hypothesis. The theoretical foundations and some applicative examples are presented. Computer programs, based on symbolic analysis techniques, are used for both the testability analysis and the neural network training phase. The obtained results are very satisfactory and demonstrate the optimal performances of the method. |
Author | Grasso, Francesco Manetti, Stefano Piccirilli, Maria Cristina Luchetta, Antonio Bindi, Marco |
Author_xml | – sequence: 1 givenname: Marco orcidid: 0000-0001-9749-602X surname: Bindi fullname: Bindi, Marco – sequence: 2 givenname: Maria Cristina orcidid: 0000-0002-9955-1990 surname: Piccirilli fullname: Piccirilli, Maria Cristina – sequence: 3 givenname: Antonio orcidid: 0000-0003-4319-1495 surname: Luchetta fullname: Luchetta, Antonio – sequence: 4 givenname: Francesco orcidid: 0000-0002-8697-2091 surname: Grasso fullname: Grasso, Francesco – sequence: 5 givenname: Stefano orcidid: 0000-0002-5798-7147 surname: Manetti fullname: Manetti, Stefano |
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SubjectTerms | Circuits Control algorithms Diagnostic tests Fault diagnosis Graphical methods Hypotheses Multilayers Neural networks Software Testability Voltage converters (DC to DC) |
Title | Testability Evaluation in Time-Variant Circuits: A New Graphical Method |
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