Three-dimensional integrated circuits

• Published in: IBM journal of research and development Vol. 50; no. 4.5; pp. 491 - 506
• Main Authors: Topol, A. W., Tulipe, D. C. La, Shi, L., Frank, D. J., Bernstein, K., Steen, S. E., Kumar, A., Singco, G. U., Young, A. M., Guarini, K. W., Ieong, M.
• Format: Journal Article
• Language: English
• Published: Armonk International Business Machines Corporation 01.07.2006
• Subjects: CMOS; Electrons; Glass substrates; Integrated circuits; Silicon wafers; Technology
• ISSN: 0018-8646; 0018-8646; 2151-8556
• DOI: 10.1147/rd.504.0491

Three-dimensional (3D) integrated circuits (ICs), which contain multiple layers of active devices, have the potential to dramatically enhance chip performance, functionality, and device packing density. They also provide for microchip architecture and may facilitate the integration of heterogeneous materials, devices, and signals. However, before these advantages can be realized, key technology challenges of 3D ICs must be addressed. More specifically, the processes required to build circuits with multiple layers of active devices must be compatible with current state-of-the-art silicon processing technology. These processes must also show manufacturability, i.e., reliability, good yield, maturity, and reasonable cost. To meet these requirements, IBM has introduced a scheme for building 3D ICs based on the layer transfer of functional circuits, and many process and design innovations have been implemented. This paper reviews the process steps and design aspects that were developed at IBM to enable the formation of stacked device layers. Details regarding an optimized layer transfer process are presented, including the descriptions of 1) a glass substrate process to enable through-wafer alignment; 2) oxide fusion bonding and wafer bow compensation methods for improved alignment tolerance during bonding; 3) and a single-damascene patterning and metallization method for the creation of high-aspect-ratio (6:1 < AR < 11:1) contacts between two stacked device layers. This process provides the shortest distance between the stacked layers (<2 µm), the highest interconnection density (>10^sup 8^ vias/cm^sup 2^), and extremely aggressive wafer-to-wafer alignment (submicron) capability. [PUBLICATION ABSTRACT]