Fine-Grain SEU Mitigation for FPGAs Using Partial TMR

• Published in: IEEE transactions on nuclear science Vol. 55; no. 4; pp. 2274 - 2280
• Main Authors: Pratt, B., Caffrey, M., Carroll, J.F., Graham, P., Morgan, K., Wirthlin, M.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.08.2008; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Aerospace industry; Circuit faults; Computer programs; Costs; fault injection; Fault tolerance; Field programmable gate arrays; field programmable gate arrays (FPGAs); Gain; Gate arrays; Laboratories; Logic design; Modular; proton accelerator; Proton accelerators; radiation effects; Redundancy; reliability; Single event upset; single-event upset (SEU); Software; Software tools; triple modular redundancy (TMR)
• ISSN: 0018-9499; 1558-1578
• DOI: 10.1109/TNS.2008.2000852

The mitigation of single-event upsets (SEUs) in field-programmable gate arrays (FPGAs) is an increasingly important subject as FPGAs are used in radiation environments such as space. Triple modular redundancy (TMR) is the most frequently used SEU mitigation technique but is very expensive in terms of area and power costs. These costs can be reduced by sacrificing some reliability and applying TMR to only part of the FPGA design. Our partial TMR method focuses on the most critical sections of the design and increases reliability by applying TMR to continuous sections of the circuit. We introduce an automated software tool that uses the Partial TMR method to apply TMR incrementally at a very fine level until the available resources are utilized. Thus the tool aims to gives the maximum reliability gain for the specified area cost.