Generation of Functional Broadside Tests for Transition Faults

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 25; no. 10; pp. 2207 - 2218
• Main Authors: Pomeranz, I., Reddy, S.M.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.10.2006; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Broadside tests; Chips; Circuit design; Circuit faults; Circuit simulation; Circuit testing; Circuits; Computer aided design; Current supplies; Design engineering; Electric potential; Electrical fault detection; Fault detection; Faults; Life testing; overtesting; Propagation delay; reachable states; Sequential analysis; transition faults; Voltage
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2005.860959

Scan design allows a circuit to be tested using states that the circuit cannot enter during functional operation. It was observed that nonfunctional operation during testing may cause excessive currents that can cause a good chip to fail the test because of voltage droops caused by the excessive current demand. A good chip may also fail due to the propagation of signal transitions along nonfunctional long paths, especially during at-speed testing. This problem is studied in this paper in the context of tests for transition faults. A method for determining transition faults that are untestable under functional operation-conditions is described. Two procedures for generating transition-fault tests that use only functional operation conditions are also described. The first procedure accepts as input a broadside test set for transition faults. The second procedure accepts as input a test sequence for the nonscan circuit. Although such a test sequence is more complex to generate and simulate, it results in higher numbers of faults detected under functional operation conditions