Pipelined Scheduling of Functional HW/SW Modules for Platform‐Based SoC Design

• Published in: ETRI journal Vol. 27; no. 5; pp. 533 - 538
• Main Authors: Kim, Wonjong, Chang, June‐Young, Cho, Hanjin
• Format: Journal Article
• Language: English
• Published: 01.10.2005
• Subjects: MPEG4; Pipelined scheduling; platform‐based SoC design
• ISSN: 1225-6463; 2233-7326
• DOI: 10.4218/etrij.05.0905.0011

We developed a pipelined scheduling technique of functional hardware and software modules for platform‐based system‐on‐a‐chip (SoC) designs. It is based on a modified list scheduling algorithm. We used the pipelined scheduling technique for a performance analysis of an MPEG4 video encoder application. Then, we applied it for architecture exploration to achieve a better performance. In our experiments, the modified SoC platform with 6 pipelines for the 32‐bit dual layer architecture shows a 118% improvement in performance compared to the given basic SoC platform with 4 pipelines for the 16‐bit single‐layer architecture.