A low power DLL based clock and data recovery circuit with wide range anti-harmonic lock

• Published in: Analog integrated circuits and signal processing Vol. 74; no. 2; pp. 355 - 364
• Main Authors: Park, Hyung-Gu, Kim, SoYoung, Lee, Kang-Yoon
• Format: Journal Article
• Language: English
• Published: Boston Springer US 01.02.2013
• Subjects: Architecture; Circuits and Systems; Clocks; Data recovery; Delay; Dynamic link libraries; Electrical Engineering; Engineering; Frequency ranges; Locks; Pulse width; Signal,Image and Speech Processing; Multi-phase; False locking problem; Delay-locked loop; Jitter; Clock and data recovery; Wide frequency range; Frequency detection
• ISSN: 0925-1030; 1573-1979
• DOI: 10.1007/s10470-012-9976-7

This paper presents a wide frequency range CDR circuit for second generation AiPi+ intra-panel interface. The speed of the proposed clock and data recovery is increased to 1.25 Gbps compared with conventional AiPi+. The DLL-based CDR architecture is adopted to generate multi-phase clocks. We propose a simple scheme for a frequency detector (FD) to overcome the limited frequency range and false lock problem of a conventional delay-locked loop (DLL) to reduce the complexity. In addition, a duty cycle corrector that limits the maximum pulse width is used to avoid the problem of missing clock edges due to the mismatches between rising and falling time of delay cells in the VCDL. Also, the proposed simple DLL architecture comprised of frequency and phase detectors has better process-portability. The proposed CDR is implemented in 0.18 μm technology and the active die area is 660 × 250 μm. The implemented DLL covers a frequency range from 62 to 128 MHz, which is limited only by the characteristics of the delay cell. The peak-to-peak jitter is less than 13 ps when the input frequency is 128 MHz, and the power consumption of the CDR except the input buffer, equalizer, and de-serializer is 5.94 mW from the supply voltage of 1.8 V.