Energy-efficient approximate full adders for error-tolerant applications

• Published in: Computers & electrical engineering Vol. 110; p. 108877
• Main Authors: Ahmadi, Farshid, Semati, Mohammad R., Daryanavard, Hassan, Minaeifar, Atefeh
• Format: Journal Article
• Language: English
• Published: Elsevier Ltd 01.09.2023
• Subjects: Approximate computing; Error report propagate full-adder; Image processing; Machine learning; Reverse carry propagate full-adder; Image processing; Approximate computing; Reverse carry propagate full-adder; Error report propagate full-adder; Machine learning
• ISSN: 0045-7906; 1879-0755
• DOI: 10.1016/j.compeleceng.2023.108877

Low-power consumption is of utmost importance in modern digital systems-on-chip. Approximate computing is a technique used in error-tolerant applications such as multimedia and machine learning to reduce power. This technique creates an appropriate trade-off between performance and accuracy. Adders, as the core of the computing blocks for many digital systems, have a significant impact on their efficiency. This paper attempts to design new approximate full adders with power as the main optimization goal. The proposed circuits are simulated with HSPICE using CMOS and FinFET technologies at 45 nm and 14 nm technology nodes respectively. The simulation results show that on average, the proposed FAs offer 18% and 22% improvements in the dynamic energy and the static power compared to their recent counterparts. Moreover, at the system level, the proposed designs provide sufficient accuracy for real computational applications such as Gaussian filter, discrete cosine transform, and k-means clustering.