An efficient parallel prefix sums architecture with domino logic

• Published in: IEEE transactions on parallel and distributed systems Vol. 14; no. 9; pp. 922 - 931
• Main Authors: Lin, R., Nakano, K., Olariu, S., Zomaya, A.Y.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.09.2003; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Arithmetic; CMOS technology; Compaction; Computer architecture; Concurrent computing; Delay; Hardware; Logic; Studies; Switches; Very large scale integration
• ISSN: 1045-9219; 1558-2183
• DOI: 10.1109/TPDS.2003.1233714

The main contribution of this work is to propose an efficient parallel prefix sums architecture based on the recently-developed technique of shift switching with domino logic, where the charge/discharge signals propagate along the switch chain producing semaphores in a network that is fast and highly hardware-compact. The proposed architecture for computing the prefix sums of N-1 bits features a total delay of (4 log N + /spl radic/N-2)/sub */T/sub d/, where T/sub d/ is the delay for charging or discharging a row of two prefix sum units of eight shift switches. Our simulation results show that, under 0.8-micron CMOS technology, the delay T/sub d/ does not exceed 1 ns. As it turns out, our design is faster than any design known to us for values on N in the range 1 /spl les/ N /spl les/ 2/sup 10/. Yet, another important and novel feature of the proposed architecture is that it requires very simple controls, partially driven by the semaphores. This significantly reduces the hardware complexity of the design and fully utilizes the inherent speed of the process.