New Erase Constraint for the Junction-Less Charge-Trap Memory Array in Cylindrical Geometry

• Published in: IEEE transactions on electron devices Vol. 60; no. 7; pp. 2203 - 2208
• Main Authors: Maconi, A., Compagnoni, C. M., Spinelli, A. S., Lacaita, A. L.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.07.2013; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Arrays; Charge-trap memories; Design. Technologies. Operation analysis. Testing; Dielectrics; Doping; Electronics; Electrostatics; erase saturation; Exact sciences and technology; flash memories; Geometry; Integrated circuits; Integrated circuits by function (including memories and processors); Logic gates; semiconductor device modeling; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Substrates; Performance evaluation; Voltage threshold; Oxide layer; Transistor gate; Multiple layer; Erasure; Cylindrical shape; Modeling; Charge-trap memories; Thickness; Semiconductor device; flash memories; Non volatile memory; Flash memory; semiconductor device modeling; Integrated circuit; erase saturation; Charge-trapping memory
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2013.2264324

This paper presents a detailed simulation analysis of the erase performance of junction-less charge-trap memory arrays in the cylindrical geometry, showing that a saturation of the erased threshold voltage occurs as a result of incomplete inversion of the intercell regions when positive charge is stored in the cells. This erase saturation issue is investigated as a function of string and cell parameters, revealing lower erase capabilities for large cell-to-cell separation, small substrate radius, and small equivalent-oxide thickness of the gate stack. These results add new constraints to the design of cylindrical junction-less memory technologies.