Study on Single Event Upset and Mitigation Technique in JLTFET‐Based 6T SRAM Cell

• Published in: Journal of Electrical and Computer Engineering Vol. 2024; no. 1
• Main Authors: K, Aishwarya, B, Lakshmi
• Format: Journal Article
• Language: English
• Published: New York John Wiley & Sons, Inc 27.09.2024; Hindawi Limited
• Subjects: Circuit design; Circuits; Current sources; Delay; Design; Error analysis; Field effect transistors; Lookup tables; Memory (Computers); Methods; Performance measurement; Power consumption; Power management; Radiation; Radiation hardening; Random access memory; Recovery time; Semiconductor devices; Simulation; Single event upsets; Soft errors; Stability; Static random access memory; Transient current; Transistors

The effect of single event transient (SET) on 6T SRAM cell employing a 20 nm silicon‐based junctionless tunneling field effect transistor (JLTFET) is explored for the first time. JLTFET‐based SRAM circuit is designed using the look up table‐based Verilog A code obtained from TCAD values of the devic...