Line and Point Tunneling in Scaled Si/SiGe Heterostructure TFETs
In this letter, we systematically investigate the impact of gate length and channel orientation on the electrical performance of tunneling field-effect transistors (TFETs). We fabricate and characterize Si/SiGe heterostructure TFETs with p-doped compressively strained Si 0.5 Ge 0.5 source, intrinsic...
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Published in | IEEE electron device letters Vol. 35; no. 7; pp. 699 - 701 |
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Main Authors | , , , , , , , |
Format | Journal Article |
Language | English |
Published |
New York, NY
IEEE
01.07.2014
Institute of Electrical and Electronics Engineers The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subjects | |
Online Access | Get full text |
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Summary: | In this letter, we systematically investigate the impact of gate length and channel orientation on the electrical performance of tunneling field-effect transistors (TFETs). We fabricate and characterize Si/SiGe heterostructure TFETs with p-doped compressively strained Si 0.5 Ge 0.5 source, intrinsic Si channel, and n-doped Si drain. We observe a linear relation of gate length, L g , and ON-current, I ON , which is the first experimental proof of line tunneling occurring in a TFET. TCAD simulations support our observations. After forming gas annealing, short-channel TFETs exhibit different I-V characteristics compared with long-channel devices due to better passivation. |
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ISSN: | 0741-3106 1558-0563 |
DOI: | 10.1109/LED.2014.2320273 |