Insights on Design and Scalability of Thin-BOX FD/SOI CMOS

• Published in: IEEE transactions on electron devices Vol. 57; no. 9; pp. 2073 - 2079
• Main Authors: Chouksey, S, Fossum, J G, Agrawal, S
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.09.2010; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; CMOS integrated circuits; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; FinFETs; General (including economical and industrial fields); high-performance (HP) CMOS; Integrated circuits; Integrated circuits by function (including memories and processors); Logic gates; low-power (LP) CMOS; MOSFET circuits; planar fully depleted (FD)/silicon-on-insulator (SOI) MOSFETs; Scalability; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicon on insulator technology; static random access memory (SRAM); Transistors; Performance evaluation; Static random access memory; MOSFET; low-power (LP) CMOS; Scalability; Random access memory; Depletion layer; high-performance (HP) CMOS; Silicon on insulator technology; Nanometer scale; static random access memory (SRAM); Non volatile memory; Complementary MOS technology; FinFETs; planar fully depleted (FD)/silicon-on-insulator (SOI) MOSFETs; Ultrathin films; High performance; Buried layer; Oxide layer; Dual gate transistor; Self aligned technology; Electronics industry; Integrated circuit; Low-power electronics; Gain; Planar technology
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2010.2052420

Device simulations are used to gain insights on the design of nanoscale thin-buried-oxide (and ultrathin-body) fully depleted/silicon-on-insulator (SOI) CMOS and to assess its scalability toward the end of the Semiconductor Industry Association roadmap (International Technology Roadmap for Semiconductors), relative to that of FinFET CMOS. The simulation results imply, albeit with complex processing, good scalability and performance for low-power (LP) applications (including static random access memory), defined by minimum viable SOI thickness. However, the scalability for high-performance (HP) applications is limited, but the processing can be simplified. Results for double-gate FinFETs are better, showing good scalability and performance to the end of the ITRS for both HP and LP applications.