Impact of TaN as Wet Etch Stop Layer on Device Characteristics for Dual-Metal HKMG Last Integration CMOSFETs

TaN as wet etch stop layer is implemented in dual-metal high- k/metal gate last integration CMOSFETs. Impacts of TaN on device characteristics are investigated. With thicker TaN, flat-band voltages (Vfb) of both n- and p-FETs shift to zero value position. Sensitivities of TaN thickness on Vfb are ob...

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Bibliographic Details
Published inIEEE electron device letters Vol. 34; no. 12; pp. 1488 - 1490
Main Authors Tang, Zhaoyun, Xu, Jing, Yang, Hong, Cui, Hushan, Tang, Bo, Xu, Yefeng, Wang, Hongli, Li, Junfeng, Yan, Jiang
Format Journal Article
LanguageEnglish
Published New York, NY IEEE 01.12.2013
Institute of Electrical and Electronics Engineers
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Applied sciences
CMOS integrated circuits
CMOSFETs
Design. Technologies. Operation analysis. Testing
Double hump
Electronics
Exact sciences and technology
flat-band voltage
High K dielectric materials
high- k /metal gate (HKMG)
Integrated circuits
Metals
MOSFET circuits
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Semiconductors
TaN
Threshold voltage
Transistors
Voltage threshold
Double hump
TaN
MOSFET
Tantalum nitride
threshold voltage
n channel
Enhancement factor
flat-band voltage
Implementation
Field effect transistor
p channel
Wet process
Complementary MOS transistor
Flat band voltage
high-k/metal gate (HKMG)
Complementary MOS technology
High k dielectric
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Summary:TaN as wet etch stop layer is implemented in dual-metal high- k/metal gate last integration CMOSFETs. Impacts of TaN on device characteristics are investigated. With thicker TaN, flat-band voltages (Vfb) of both n- and p-FETs shift to zero value position. Sensitivities of TaN thickness on Vfb are obtained with 81 and -114 mV/nm for n- and p-FETs, respectively. It could be served as an important enhancement tuning factor for threshold voltage (Vth) adjustment in CMOSFETs due to contributions of TaN on Vth values are in the same direction. With CMOS technology moving to below 22-nm node, it is crucial to control amount of wet etch of TaN layer, otherwise device characteristics would be impacted and double hump happens.
ISSN:0741-3106
1558-0563
DOI:10.1109/LED.2013.2287271