High yielding self-aligned contact process for a 0.150-μm DRAM technology

• Published in: IEEE transactions on semiconductor manufacturing Vol. 15; no. 2; pp. 223 - 228
• Main Authors: RUPP, Thomas S, DOBUZINSKY, David, ZHIJIAN LU, SARDESAI, Viraj Y, LIU, Hang-Yip, MALDEI, Michael, FALTERMEIER, John, GAMBINO, Jeff
• Format: Journal Article
• Language: English
• Published: New York, NY Institute of Electrical and Electronics Engineers 01.05.2002
• Subjects: Applied sciences; Aspect ratio; Contact; Dynamic random access memory; Electronics; Etching; Exact sciences and technology; Gates; Grounds; Integrated circuits; Integrated circuits by function (including memories and processors); Lithography; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Semiconductors; Microelectronic fabrication; Reactive ion etching; Random access memory; Dynamical storage; Selective etching; Contact process; Self aligned technology
• ISSN: 0894-6507; 1558-2345
• DOI: 10.1109/66.999596

This paper describes improvements in the self-aligned contact process for 0.150 mu m and 0.175 mu m technology generations. Using a dynamic random access memory cell layout, we show that self-aligned contacts can be formed at 0.175 mu m ground rules and beyond by using a C sub(4)F sub(8)-CH sub(2)F sub(2) chemistry. With the improved etch selectivity, gate cap nitride thickness can be reduced, resulting in a smaller aspect ratio for the gate etch, borophosphosilicate glass fill, and contact etch. With a rectangular contact, the area can be increased and the process windows for lithography and etch are improved. The process window for lithography increases by up to 40%, the aspect ratio for the etch and the contact fill is less, and the sensitivity to misalignment is reduced. The combination of rectangular contacts and C sub(4)F sub(8)-CH sub(2)F sub(2) chemistry greatly enhances the product yield