RS-FDRA: A register-sensitive software pipelining algorithm for embedded VLIW processors

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 21; no. 12; pp. 1395 - 1415
• Main Authors: Akturan, C., Jacome, M.F.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.12.2002; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Computer programs; Constraint optimization; Degradation; Delay; Embedded software; Exploration; Optimization; Optimizing compilers; Pipeline processing; Pipelining (computers); Processors; Registers; Software; Software algorithms; Time factors; VLIW
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2002.804373

The paper proposes a novel software-pipelining algorithm, Register-Sensitive Force-Directed Retiming Algorithm (RS-FDRA), suitable for optimizing compilers targeting embedded very large instruction word processors. The key difference between RS-FDRA and previous approaches is that this algorithm can handle code-size constraints along with latency and resource constraints. This capability enables the exploration of Pareto "optimal" points with respect to code size and performance. RS-FDRA can also minimize the increase in register pressure typically incurred by software pipelining. This ability is critical since the need to insert spill code may result in significant performance degradation. Extensive experimental results are presented demonstrating that the extended set of optimization goals and constraints supported by RS-FDRA enables a thorough compiler-assisted exploration of tradeoffs among performance, code size, and register requirements for time-critical segments of embedded software components.