An efficient power reduction technique for CMOS flash analog-to-digital converters

• Published in: Analog integrated circuits and signal processing Vol. 61; no. 3; pp. 271 - 278
• Main Authors: Hwang, Yuh-Shyan, Huang, Po-Hsiang, Hwang, Bo-Han, Chen, Jiann-Jong
• Format: Journal Article
• Language: English
• Published: Boston Springer US 01.12.2009
• Subjects: Analog to digital conversion; Circuits and Systems; CMOS; Coarsening; Comparators; Converters; Electrical Engineering; Engineering; Power consumption; Reduction; Signal,Image and Speech Processing; Voltage; Analog-to-digital converter; Flash ADC; Power reduction
• ISSN: 0925-1030; 1573-1979
• DOI: 10.1007/s10470-009-9309-7

An efficient power reduction technique for CMOS flash analog-to-digital converter (ADC) is presented. The presented technique adopts the procedure with a simple coarse comparison first followed by a finer comparison later. Our ADC design does not decrease the total number of comparators, though it is able to reduce the power consumption. Subject to time signal controlling, the manipulation is to interchangeably shut down the comparator sections for the coarse comparison function. Experimental results show that this new method consumes about 48.14 mW at 400 MHz with 3.3 V supply voltage in TSMC 0.35 μm 2P4 M process. Compared with the traditional flash ADC, our low power method can reduce up to 47.8% in power consumption. The DNL of our proposed flash ADC is 0.5 LSB, the INL is 0.7 LSB, and the ENOB is 5.75 bits. The chip area occupies 0.4 × 0.9 mm 2 without I/O pads.