Region-based parallelization of irregular reductions on explicitly managed memory hierarchies

• Published in: The Journal of supercomputing Vol. 56; no. 1; pp. 25 - 55
• Main Authors: Kim, Seonggun, Han, Hwansoo, Choe, Kwang-Moo
• Format: Journal Article
• Language: English
• Published: Boston Springer US 01.04.2011
• Subjects: Bandwidth; Compilers; Computation; Computer programs; Computer Science; Hierarchies; Interpreters; Parallel processing; Processor Architectures; Programming Languages; Reduction; Scheduling; Tasks; Irregular reduction; Explicitly managed memory hierarchies; Loop parallelization; Compilation techniques
• ISSN: 0920-8542; 1573-0484
• DOI: 10.1007/s11227-009-0340-3

Multicore architectures are evolving with the promise of extreme performance for the classes of applications that require high performance and large bandwidth of memory. Irregular reduction is one of important computation patterns for many complex scientific applications, and it typically requires high performance and large bandwidth of memory. In this article, we propose region-based parallelization techniques for irregular reductions on multicore architectures with explicitly managed memory hierarchies. Managing memory hierarchy in software requires a lot of programming efforts and tends to be error-prone. The difficulties are even worse for applications with irregular data access patterns. To relieve the burden of memory management from programmers, we develop abstractions, particularly targeted to irregular reduction, for structuring parallel tasks, mapping the parallel tasks to processing units and scheduling data transfers between the memory hierarchies. Our framework employs iteration reordering based on regions of data along with dynamic scheduling of parallel tasks. We experimentally evaluate the effectiveness of our techniques for irregular reduction kernels on the Cell processor embedded in a Sony PlayStation3. Experimental results show the speedups of 8 to 14 on the six available SPEs.