A novel parallel prefix adder for optimized Radix-2 FFT processor

• Published in: Multidimensional systems and signal processing Vol. 32; no. 3; pp. 1041 - 1063
• Main Authors: Thakur, Garima, Sohal, Harsh, Jain, Shruti
• Format: Journal Article
• Language: English
• Published: New York Springer US 01.07.2021; Springer Nature B.V
• Subjects: Algorithms; Artificial Intelligence; Circuits and Systems; Computer architecture; Delay; Electrical Engineering; Engineering; Fast Fourier transformations; Fourier transforms; Microprocessors; Power management; Resource utilization; Signal,Image and Speech Processing; Radix 2 structure; FFT algorithm; PP adders; Wallace multiplier
• ISSN: 0923-6082; 1573-0824
• DOI: 10.1007/s11045-021-00772-1

The Fast Fourier Transform (FFT) is the basic building block for DSP applications where high processing speed is the critical requirement. Resource utilization and the number of computational stages in Radix-2 FFT structure implementation can be minimized by improving the performance of utilized multiplier and adder blocks. This work proposes a hardware design of an efficient Radix-2 FFT architecture using optimized multiplier and novel Parallel prefix (PP) adder. The designed FFT architecture results in low power and area with an increase in operation speed in comparison to the existing architectures. Our proposed Radix 2 FFT implementation results in 18.218 ns (6.030 ns logic delay and 12.118 ns router delay) in comparison with 24.003 ns delay for Wallace multiplier using Kogge Stone PP adder (M1P1), 24.162 ns delay for Wallace multiplier using Brent Kung PP adder (M2P2), 24.889 ns delay for Wallace multiplier using Landner Fischer PP adder (M3P3) and 22.827 ns delay for Wallace multiplier using Han Carlson PP adder (M4P4) algorithm. The proposed adder and hence the FFT processor can be used in different applications where high speed, low power, and less area is required. The novel PP architecture results in a 20.19% improvement in comparison with other state-of-art techniques.