A maskable memory architecture for rank-order filtering

• Published in: IEEE transactions on consumer electronics Vol. 50; no. 2; pp. 558 - 564
• Main Authors: Dung, Lan-Rong, Lin, Meng-Chun
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.05.2004; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: CADCAM; Computer aided manufacturing; Costs; Filtering algorithms; Hardware; Memory architecture; Nonlinear filters; Polarization; Signal processing algorithms; Sorting
• ISSN: 0098-3063; 1558-4127
• DOI: 10.1109/TCE.2004.1309423

This paper presents a novel implementation of rank-order filtering using maskable memory. Based on a generic bit-sliced rank-order filtering algorithm the proposed design uses a special-defined memory, called parallel maskable memory (PMM) to realize major operations of rank-order filtering, threshold decomposition and polarization. In conventional designs, these operations are usually implemented as logic circuit and require complex computation. Using the memory-oriented architecture, the proposed rank-order filter can benefit from high flexibility, low cost and high speed. PMM has features of bit-sliced read, partial write, and pipelined processing. Bit-sliced read and partial write are driven by maskable registers. The maskable registers allows PMM to configure operating bits for parallel read/write operations. Combining the bit-sliced read with polarization selector allows PMM to perform polar determination while the partial write achieves polarization. Recursively combining the bit-sliced read and partial write, PMM can effectively realizes rank-order filtering in terms of cost and speed.