Intelligent Signal Gating-Aware Energy-Efficient 8-Bit FinFET Arithmetic and Logic Unit

• Published in: Circuits, systems, and signal processing Vol. 41; no. 1; pp. 299 - 320
• Main Authors: Ajitha, D., Chandra Sekhar Reddy, M.
• Format: Journal Article
• Language: English
• Published: New York Springer US 2022; Springer Nature B.V
• Subjects: Adding circuits; Arithmetic and logic units; Circuits; Circuits and Systems; CMOS; Design; Electrical Engineering; Electronics and Microelectronics; Energy; Engineering; Instrumentation; Power consumption; Scientific papers; Signal processing; Signal,Image and Speech Processing; Transistors; Intelligent signal gating; Low-power ALU; GDI-FinFET; Hybrid full adder
• ISSN: 0278-081X; 1531-5878
• DOI: 10.1007/s00034-021-01775-w

A FinFET-based 8-bit low-power arithmetic and logic unit (ALU) with full-swing 9-transistor GDI-hybrid full adder has been presented in this research paper. An intelligent signal gating-aware energy-efficient ALU is proposed using this adder and signal gating circuit. An adaptive signal gating is applied according to the current ALU operation based on the particular operation corresponding control word. The input signals to the other blocks are gated such that the proposed intelligent signal gating scheme customizes the overall power utilization of the proposed ALU. The proposed ALU has been implemented using 20 nm FinFET PTM models. The total power consumption of the conventional FinFET ALU to execute all eight operations is 619.55 µW, whereas the proposed ALU consumes 225.53 µW only. The average power consumption of the traditional FinFET ALU is 77.44 µW per operation, while the proposed low-power ALU needs 28.19 µW only. The maximum amount of total and average power that the proposed scheme can optimize is 63.59%.