Chip Size Minimization for Wide and Ultrawide Bandgap Power Devices

• Published in: IEEE transactions on electron devices Vol. 70; no. 2; pp. 1 - 7
• Main Authors: Wang, Boyan, Xiao, Ming, Zhang, Zichen, Wang, Yifan, Qin, Yuan, Song, Qihao, Lu, Guo-Quan, Ngo, Khai, Zhang, Yuhao
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.02.2023; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Aluminum nitride; Chip size; codesign; Cost analysis; Design optimization; Diamonds; drift region; Electronic devices; Energy gap; Engineering; III-V semiconductor materials; Multichip modules; packaging; Photonic band gap; Physics; power devices; power electronics; power loss; Silicon; Silicon carbide; Switches; Switching; switching frequency; Thermal management; ultrawide bandgap; wide bandgap (WBG)
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2022.3232309

Chip size (<inline-formula> <tex-math notation="LaTeX">\textit{A}_{\text{chip}}</tex-math> </inline-formula>) optimization is key to the accurate analysis of device and material costs and the design of multichip modules. It is particularly critical for wide bandgap (WBG) and ultrawide bandgap (UWBG) power devices due to high material cost. Moreover, the designs of <inline-formula> <tex-math notation="LaTeX">\textit{A}_{\text{chip}}</tex-math> </inline-formula> and the drift region thickness (<inline-formula> <tex-math notation="LaTeX">\textit{W}_{\text{dr}}</tex-math> </inline-formula>) and doping concentration (<inline-formula> <tex-math notation="LaTeX">\textit{N}_{\text{dr}}</tex-math> </inline-formula>) are interdependent, requiring their co-optimization. Current design practices for <inline-formula> <tex-math notation="LaTeX">\textit{A}_{\text{chip}}</tex-math> </inline-formula>, <inline-formula> <tex-math notation="LaTeX">\textit{W}_{\text{dr}}</tex-math> </inline-formula>, and <inline-formula> <tex-math notation="LaTeX">\textit{N}_{\text{dr}}</tex-math> </inline-formula> rely on optimizing electrical parameters.<inline-formula> <tex-math notation="LaTeX">^{^{^{}}}</tex-math> </inline-formula> This work presents a new, holistic, electrothermal approach to optimize <inline-formula> <tex-math notation="LaTeX">\textit{A}_{\text{chip}}</tex-math> </inline-formula> for a given set of target specifications, including breakdown voltage (BV), conduction current (<inline-formula> <tex-math notation="LaTeX">\textit{I}_{\text{0}}</tex-math> </inline-formula>), and switching frequency (<inline-formula> <tex-math notation="LaTeX">\textit{f}</tex-math> </inline-formula> ). The conduction and switching losses of the device are considered as well as the heat dissipation in the chip and its package. For a given BV and <inline-formula> <tex-math notation="LaTeX">\textit{I}_{\text{o}}</tex-math> </inline-formula>, the optimal <inline-formula> <tex-math notation="LaTeX">\textit{A}_{\text{chip}}</tex-math> </inline-formula>, <inline-formula> <tex-math notation="LaTeX">\textit{W}_{\text{dr}}</tex-math> </inline-formula>, and <inline-formula> <tex-math notation="LaTeX">\textit{N}_{\text{dr}}</tex-math> </inline-formula> show a strong dependence on <inline-formula> <tex-math notation="LaTeX">\textit{f}</tex-math> </inline-formula> and thermal management. Such dependencies are missing in prior <inline-formula> <tex-math notation="LaTeX">\textit{A}_{\text{chip}}</tex-math> </inline-formula> design methods. This approach is applied to compare the optimal <inline-formula> <tex-math notation="LaTeX">\textit{A}_{\text{chip}}</tex-math> </inline-formula> of WBG and UWBG devices up to a BV over 10 kV and <inline-formula> <tex-math notation="LaTeX">\textit{f}</tex-math> </inline-formula> of 1 MHz.<inline-formula> <tex-math notation="LaTeX">^{^{^{}}}</tex-math> </inline-formula> Our approach offers more accurate cost analysis and design guidelines for power modules.