Serial/Parallel Convolvers

• Published in: IEEE transactions on computers Vol. C-33; no. 7; pp. 652 - 667
• Main Author: Danielsson, Per E.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.07.1984; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Arrays; Bit-serial processing; Circuit properties; Clocks; Convolution; Convolvers; Data mining; Delay; Digital circuits; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Indexes; recursive filter design; serial/parallel multipliers; signal processing; systolic arrays; VLSI design; Series parallel connection; VLSI circuit; Circuit design; Image processing; Convolution circuit; Parallel processing; Signal processing; Recursive filter
• ISSN: 0018-9340; 1557-9956
• DOI: 10.1109/TC.1984.5009339

A new type of convolver is presented. This type utilizes a kind of systolic array where the basic cell is mainly a full adder and the basic structure is a serial/parallel multiplier. A new formalism is developed which encompasses the whole family of serial/parallel multipliers. All these designs can be carried over to the design of convolvers since the convolution formula has the same structure on the word level as the multiplier on the bit level. Furthermore, the whole convolver can be embedded in one single uniform bit-serial one-dimensional structure. This extremely pin-saving and VLSI-oriented design can also be used for recursive filters and for 2D signal processing. Programmability (using a structure with varying precision and kernel size) can be traded for simplicity and efficacy. The paper contains comparative discussions of other convolvers; however, actual hardware performance is not given.