Abelian Logic Gates

• Published in: Combinatorics, probability & computing Vol. 28; no. 3; pp. 388 - 422
• Main Authors: HOLROYD, ALEXANDER E., LEVINE, LIONEL, WINKLER, PETER
• Format: Journal Article
• Language: English
• Published: Cambridge, UK Cambridge University Press 01.05.2019
• Subjects: Integers; Linear functions; Logic circuits; Microprocessors; Periodic functions; Processors; Quotients; 90B10; Secondary 68Q45; Primary 68Q10; 68Q85
• ISSN: 0963-5483; 1469-2163
• DOI: 10.1017/S0963548318000482

An abelian processor is an automaton whose output is independent of the order of its inputs. Bond and Levine have proved that a network of abelian processors performs the same computation regardless of processing order (subject only to a halting condition). We prove that any finite abelian processor can be emulated by a network of certain very simple abelian processors, which we call gates. The most fundamental gate is a toppler, which absorbs input particles until their number exceeds some given threshold, at which point it topples, emitting one particle and returning to its initial state. With the exception of an adder gate, which simply combines two streams of particles, each of our gates has only one input wire, which sends letters (‘particles’) from a unary alphabet. Our results can be reformulated in terms of the functions computed by processors, and one consequence is that any increasing function from ℕk to ℕℓ that is the sum of a linear function and a periodic function can be expressed in terms of (possibly nested) sums of floors of quotients by integers.