Response compaction for system-on-a-chip based on advanced convolutional codes
This paper addresses the problem of test response compaction. In order to maximize compaction ratio, a single-output compactor based on a (n, n-1, m, 3) convolutional code is presented. When the proposed theorems are satisfied, the compactor can avoid two and any odd erroneous bits cancellations, an...
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Published in | Science China. Information sciences Vol. 49; no. 2; pp. 262 - 272 |
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Main Authors | , , , |
Format | Journal Article |
Language | English |
Published |
Heidelberg
Springer Nature B.V
01.04.2006
Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100080, China Graduate University of Chinese Academy of Sciences, Beijing 100039, China%Synopsys, Inc., 700 E. Middlefield Rd., Mountain View, CA 94043, USA |
Subjects | |
Online Access | Get full text |
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Summary: | This paper addresses the problem of test response compaction. In order to maximize compaction ratio, a single-output compactor based on a (n, n-1, m, 3) convolutional code is presented. When the proposed theorems are satisfied, the compactor can avoid two and any odd erroneous bits cancellations, and handle one unknown bit (X bit). When the X bits in response are clustered, multiple-weight check matrix design algorithm can be used to reduce the effect of massive X bits. Some extended experimental results show that the proposed encoder has an acceptable-level X tolerant capacity and low error cancellations probability. |
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Bibliography: | TP301 SOC test, response compaction, convolutional code, aliasing, X bits masking. 11-4426/N ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 23 |
ISSN: | 1009-2757 1674-733X 1862-2836 1869-1919 |
DOI: | 10.1007/s11432-006-0262-0 |