Bit-level two's complement matrix multiplication

• Published in: Integration (Amsterdam) Vol. 33; no. 1; pp. 3 - 21
• Main Authors: Grover, Radhika S., Shang, Weijia, Li, Qiang
• Format: Journal Article
• Language: English
• Published: Amsterdam Elsevier B.V 01.12.2002; Elsevier Science
• Subjects: Applied sciences; Bit-level; Circuit properties; Digital circuits; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Mapping algorithms to hardware; Matrix multiplication; Reconfigurable computing; Reconfigurable computing; Bit-level; Matrix multiplication; Mapping algorithms to hardware; Circuit design; Multiplier; Matrix product; Digital circuit; Fixed point
• ISSN: 0167-9260; 1872-7522
• DOI: 10.1016/S0167-9260(02)00020-2

We present a novel design of a bit-level matrix multiplier in which individual bits of a word do not have to be processed as a unit. In bit-level architectures the carry propagation delay is eliminated from the critical path. For example, in matrix multiplication, the carry chain of calculating the product of two numbers is broken by sending the partial sums and carries of the product to the accumulating operation instead of the whole finished word. In contrast, in a word-level matrix multiplier a product of two words has to be computed completely before it can be added to the next word-level product. Bit-level architectures for fixed-point matrix multiplication are proven to be O( log p) times faster than the corresponding word-level architecture, where p is the word length. The design is modified from our previous work to handle two's complement numbers as well. The design procedure is shown in detail by presenting the dependence graph, time and space mappings of our design. In addition, the time optimality and conflict-free properties of the design are also proven.