Covert Timing Channels Exploiting Cache Coherence Hardware: Characterization and Defense

• Published in: International journal of parallel programming Vol. 47; no. 4; pp. 595 - 620
• Main Authors: Yao, Fan, Doroslovački, Miloš, Venkataramani, Guru
• Format: Journal Article
• Language: English
• Published: New York Springer US 01.08.2019; Springer Nature B.V
• Subjects: Channels; Coherence; Computer Science; Hardware; Processor Architectures; Protocol (computers); Snoopy protocols; Software Engineering/Programming and Operating Systems; Theory of Computation; Information leakage; Cache coherence protocols; Hardware security; Hardware defense; Covert timing channels

Information leakage of sensitive data has become one of the fast growing concerns among computer users. With adversaries turning to hardware for exploits, caches are frequently a target for timing channels since they present different timing profiles for cache miss and hit latencies. Such timing cha...