Covert Timing Channels Exploiting Cache Coherence Hardware: Characterization and Defense

• Published in: International journal of parallel programming Vol. 47; no. 4; pp. 595 - 620
• Main Authors: Yao, Fan, Doroslovački, Miloš, Venkataramani, Guru
• Format: Journal Article
• Language: English
• Published: New York Springer US 01.08.2019; Springer Nature B.V
• Subjects: Channels; Coherence; Computer Science; Hardware; Processor Architectures; Protocol (computers); Snoopy protocols; Software Engineering/Programming and Operating Systems; Theory of Computation; Information leakage; Cache coherence protocols; Hardware security; Hardware defense; Covert timing channels
• ISSN: 0885-7458; 1573-7640
• DOI: 10.1007/s10766-018-0608-4

Information leakage of sensitive data has become one of the fast growing concerns among computer users. With adversaries turning to hardware for exploits, caches are frequently a target for timing channels since they present different timing profiles for cache miss and hit latencies. Such timing channels operate by having an adversary covertly communicate secrets to a spy simply through modulating resource timing without leaving any physical evidence. In this article, we demonstrate a new vulnerability exposed by cache coherence protocols where adversaries could manipulate the coherence states on certain cache blocks to alter cache access timing and communicate secrets illegitimately. Our threat model assumes the trojan and spy can either exploit explicitly shared read-only physical pages (e.g., shared library code), or use memory deduplication feature to implicitly force create shared physical pages. We demonstrate a template that adversaries may use to construct covert timing channels through manipulating combinations of coherence states and data placement in different caches. We investigate several classes of cache coherence protocols, and observe that both directory-based and snoopy protocols can be subject to covert timing channel attacks. We identify that the root cause of the vulnerability to be the existence of access latency difference for cache lines in read-only cache coherence states: Exlusive and Shared . For defense, we propose a slightly modified cache coherence scheme that will enable the last level cache to directly respond to read data requests in these read-only coherence states, and avoid any latency difference that could enable timing channels.