Estimation and Analysis of Novel Dynamic Body Biased TSPC Design Technique

This paper targets to present energy efficient high speed true single phase clock dynamic circuit design technique, utilizing a novel body biasing tuner. The threshold voltage is controlled dynamically by dint of a novel body bias tuner so that performance of the circuit is enhanced in terms of powe...

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Bibliographic Details
Published inMĀPAN : journal of Metrology Society of India Vol. 33; no. 4; pp. 405 - 416
Main Authors Verma, Preeti, Pandey, Vinay S., Sharma, Ajay K., Noor, Arti
Format Journal Article
LanguageEnglish
Published New Delhi Springer India 01.12.2018
Springer Nature B.V
Subjects
Bias
Circuit design
Computer simulation
Delay
Energy conservation
Mathematical and Computational Physics
Mathematical Methods in Physics
Measurement Science and Instrumentation
Noise
Numerical and Computational Physics
Original Paper
Physics
Physics and Astronomy
Power consumption
Prolongation
Simulation
Theoretical
Threshold voltage
Low power
Dynamic logic
Bouncing noise
TSPC
Delay
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Summary:This paper targets to present energy efficient high speed true single phase clock dynamic circuit design technique, utilizing a novel body biasing tuner. The threshold voltage is controlled dynamically by dint of a novel body bias tuner so that performance of the circuit is enhanced in terms of power, delay, temperature, voltage, noise and corner variations. Power consumption and delay is computed and analysed for wide range of temperature and 40.78–95.5% saving in power delay product is obtained with the same. Quantification of bias voltage variation effect and process corners to find the effectiveness of the proposed design are examined and it is found to be performing consistently as compared with other techniques. Later on bouncing noise analysis is done for the valuation of noise in the circuit. Comparison of power delay product, transistor count and clock phase is done with several previously reported designs. Comprehensive simulation in cadence using 90 nm technology, shows that the proposed design vanquish conventional and other previously reported dynamic circuit design techniques in all aspect of circuit performance. Further, an arithmetic logic unit for measurement using sensors is implemented as a prolongation of the proposed dynamic circuit design technique.
ISSN:0970-3950
0974-9853
DOI:10.1007/s12647-018-0275-3