Reliable high-yield CNTFET-based 9T SRAM operating near threshold voltage region

• Published in: Journal of computational electronics Vol. 17; no. 2; pp. 774 - 783
• Main Authors: Patel, Pramod Kumar, Malik, M. M., Gupta, Tarun K.
• Format: Journal Article
• Language: English
• Published: New York Springer US 01.06.2018; Springer Nature B.V
• Subjects: Access time; Carbon nanotubes; Electrical Engineering; Engineering; Field effect transistors; Leakage current; Mathematical and Computational Engineering; Mathematical and Computational Physics; Mechanical Engineering; Optical and Electronic Materials; Power consumption; Power management; Semiconductor devices; Static random access memory; Theoretical; Threshold voltage; Transistors; High yield; Carbon nanoelectronics; CNTFET technology; Near threshold voltage; Probability of functionality
• ISSN: 1569-8025; 1572-8137
• DOI: 10.1007/s10825-017-1127-z

We propose a reliable high-yield nine-carbon-nanotube field-effect transistor (9-CNTFET) static random-access memory (SRAM) cell using shared bit line and half-select-free techniques. The proposed SRAM cell operates near the threshold voltage of 325 mV. The proposed cell was also tested and verified under process variation, exhibiting stable write and read operations. Due to the reduced leakage current of the proposed cell, the power consumption is significantly decreased by 4.98-fold compared with the conventional six-transistor (6T) cell. Although the use of a CNT array increases the probability of functionality of the CNTFET, it occupies 1 % more area. Due to its high I ON / I OFF ratio, shortest node, shared bit line, and high-efficiency read and write ports, the read and write access time of the proposed nine-transistor (9T) SRAM cell is improved by 43 and 98 %, respectively, compared with the conventional 6T device. When using the low-feature-size CNTFET device in a new 9T SRAM cell, the area overhead is reduced to 32.9 % compared with previously published 9T SRAM cells. The proposed cell operates with minimum supply voltage near the threshold voltage region, reducing the read and write power consumption per bit by 1.2- and 1.8-fold, respectively, compared with existing 9T SRAM cells.