Automatic Identification of Customized Instruction Based on Multiple Attribute Decision-Making for Multi-Issue Architectures

This paper illustrates the importance of the configuration of function units and the change of an application’s critical path when using instruction set extension (ISE) with multi-issue architectures. This paper also presents an automatic identification approach for customized instruction without in...

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Bibliographic Details
Published inTsinghua science and technology Vol. 16; no. 3; pp. 278 - 284
Main Author 谭洪贺 孙义和
Format Journal Article
LanguageEnglish
Chinese
Published Elsevier Ltd 01.06.2011
Tsinghua National Laboratory of Information and Technology, Institute of Microelectronics, Tsinghua University, Beijing 100084, China
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Summary:This paper illustrates the importance of the configuration of function units and the change of an application’s critical path when using instruction set extension (ISE) with multi-issue architectures. This paper also presents an automatic identification approach for customized instruction without input/output number constraints for multi-issue architectures. The approach identifies customized instructions using multiple attribute decision-making based on the analysis of several attributes for each candidate node. Tests indicate that the approach achieves higher speedup ratios than previous approaches, as well as less area cost. In addition, this approach provides designers with multiple candidate designs.
Bibliography:11-3745/N
instruction set extension (ISE); multi-issue architecture; customized instruction (CI)
This paper illustrates the importance of the configuration of function units and the change of an application’s critical path when using instruction set extension (ISE) with multi-issue architectures. This paper also presents an automatic identification approach for customized instruction without input/output number constraints for multi-issue architectures. The approach identifies customized instructions using multiple attribute decision-making based on the analysis of several attributes for each candidate node. Tests indicate that the approach achieves higher speedup ratios than previous approaches, as well as less area cost. In addition, this approach provides designers with multiple candidate designs.
TAN Honghe , SUN Yihe Tsinghua National Laboratory of Information and Technology, Institute of Microelectronics, Tsinghua University, Beijing 100084, China
ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:1007-0214
1878-7606
1007-0214
DOI:10.1016/S1007-0214(11)70040-2