Charge trapping in surface accumulation layer of heavily doped junctionless nanowire transistors
We investigate the conductivity characteristics in the surface accumulation layer of a junctionless nanowire transistor fabricated by the femtosecond laser lithography on a heavily n-doped silicon-on-insulator wafer. The conductivity of the accumulation region is totally suppressed when the gate vol...
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Published in | Chinese physics B Vol. 24; no. 12; pp. 587 - 591 |
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Main Author | |
Format | Journal Article |
Language | English |
Published |
01.12.2015
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Subjects | |
Online Access | Get full text |
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