Charge trapping in surface accumulation layer of heavily doped junctionless nanowire transistors

We investigate the conductivity characteristics in the surface accumulation layer of a junctionless nanowire transistor fabricated by the femtosecond laser lithography on a heavily n-doped silicon-on-insulator wafer. The conductivity of the accumulation region is totally suppressed when the gate vol...

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Published inChinese physics B Vol. 24; no. 12; pp. 587 - 591
Main Author 马刘红 韩伟华 王昊 杨香 杨富华
Format Journal Article
LanguageEnglish
Published 01.12.2015
Subjects
Charge
Drains
Electric potential
Nanowires
Scattering
Transistors
Trapping
Voltage
俘获效应
晶体管
激光光刻技术
电子迁移率
界面电荷
纳米线
表面层
重掺杂
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Abstract We investigate the conductivity characteristics in the surface accumulation layer of a junctionless nanowire transistor fabricated by the femtosecond laser lithography on a heavily n-doped silicon-on-insulator wafer. The conductivity of the accumulation region is totally suppressed when the gate voltage is more positive than the flatband voltage. The extracted low field electron mobility in the accumulation layer is estimated to be 1.25 cm^2·V^-1·s^-1. A time-dependent drain current measured at 6 K predicts the existence of a complex trap state at the Si–Si O2 interface within the bandgap. The suppressed drain current and comparable low electron mobility of the accumulation layer can be well described by the large Coulomb scattering arising from the presence of a large density of interface charged traps. The effects of charge trapping and the scattering at interface states become the main reasons for mobility reduction for electrons in the accumulation region.
AbstractList We investigate the conductivity characteristics in the surface accumulation layer of a junctionless nanowire transistor fabricated by the femtosecond laser lithography on a heavily n-doped silicon-on-insulator wafer. The conductivity of the accumulation region is totally suppressed when the gate voltage is more positive than the flatband voltage. The extracted low field electron mobility in the accumulation layer is estimated to be 1.25 cm super(2)[middot]V super(-1)[middot]s super(-1). A time-dependent drain current measured at 6 K predicts the existence of a complex trap state at the Si-SiO sub(2) interface within the bandgap. The suppressed drain current and comparable low electron mobility of the accumulation layer can be well described by the large Coulomb scattering arising from the presence of a large density of interface charged traps. The effects of charge trapping and the scattering at interface states become the main reasons for mobility reduction for electrons in the accumulation region.
We investigate the conductivity characteristics in the surface accumulation layer of a junctionless nanowire transistor fabricated by the femtosecond laser lithography on a heavily n-doped silicon-on-insulator wafer. The conductivity of the accumulation region is totally suppressed when the gate voltage is more positive than the flatband voltage. The extracted low field electron mobility in the accumulation layer is estimated to be 1.25 cm^2·V^-1·s^-1. A time-dependent drain current measured at 6 K predicts the existence of a complex trap state at the Si–Si O2 interface within the bandgap. The suppressed drain current and comparable low electron mobility of the accumulation layer can be well described by the large Coulomb scattering arising from the presence of a large density of interface charged traps. The effects of charge trapping and the scattering at interface states become the main reasons for mobility reduction for electrons in the accumulation region.
Author 马刘红 韩伟华 王昊 杨香 杨富华
AuthorAffiliation Engineering Research Center for Semiconductor Integration Technology, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, China
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Notes We investigate the conductivity characteristics in the surface accumulation layer of a junctionless nanowire transistor fabricated by the femtosecond laser lithography on a heavily n-doped silicon-on-insulator wafer. The conductivity of the accumulation region is totally suppressed when the gate voltage is more positive than the flatband voltage. The extracted low field electron mobility in the accumulation layer is estimated to be 1.25 cm^2·V^-1·s^-1. A time-dependent drain current measured at 6 K predicts the existence of a complex trap state at the Si–Si O2 interface within the bandgap. The suppressed drain current and comparable low electron mobility of the accumulation layer can be well described by the large Coulomb scattering arising from the presence of a large density of interface charged traps. The effects of charge trapping and the scattering at interface states become the main reasons for mobility reduction for electrons in the accumulation region.
11-5639/O4
junctionless nanowire transistors,trap,femtosecond laser lithography,electron mobility
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SubjectTerms Charge
Drains
Electric potential
Nanowires
Scattering
Transistors
Trapping
Voltage
俘获效应
晶体管
激光光刻技术
电子迁移率
界面电荷
纳米线
表面层
重掺杂
Title Charge trapping in surface accumulation layer of heavily doped junctionless nanowire transistors
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