Fault Injection in Modern Microprocessors Using On-Chip Debugging Infrastructures

In this paper, a new fault injection approach to measure SEU sensitivity in COTS microprocessors is presented. It consists in a hardware-implemented module that performs fault injection through the available JTAG-based On-Chip Debugger (OCD). This approach can be applied to most microprocessors, sin...

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Bibliographic Details
Published inIEEE transactions on dependable and secure computing Vol. 8; no. 2; pp. 308 - 314
Main Authors Portela-García, Marta, López-Ongil, Celia, Valderas, Mario García, Entrena, L
Format Journal Article
LanguageEnglish
Published Washington IEEE 01.03.2011
IEEE Computer Society
Subjects
Analysis
Circuit faults
Circuits
Communication systems
Computer programs
COTS microprocessors
Debugging
Design
Digital Object Identifier
fault injection
Fault tolerance
Faults
Field programmable gate arrays
Hardware
Methods
Microprocessors
Program processors
Radiation
Registers
Sensitivity
Simulation
single event upset
soft errors
Software
Studies
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Summary:In this paper, a new fault injection approach to measure SEU sensitivity in COTS microprocessors is presented. It consists in a hardware-implemented module that performs fault injection through the available JTAG-based On-Chip Debugger (OCD). This approach can be applied to most microprocessors, since JTAG standard is a widely supported interface and OCDs are usually available in current microprocessors. Hardware implementation avoids the communication between the target system and the software debugging tool, increasing significantly the fault injection efficiency. The method has been applied to a complex microprocessor (ARM). Experimental results demonstrate the approach is a fast, efficient, and cost-effective solution.
Bibliography:ObjectType-Article-1
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ISSN:1545-5971
1941-0018
DOI:10.1109/TDSC.2010.50