Low-Temperature, Strong SiO2-SiO2 Covalent Wafer Bonding for III–V Compound Semiconductors-to-Silicon Photonic Integrated Circuits

• Published in: Journal of electronic materials Vol. 37; no. 10; pp. 1552 - 1559
• Main Authors: Liang, Di, Fang, Alexander W., Park, Hyundai, Reynolds, Tom E., Warner, Keith, Oakley, Douglas C., Bowers, John E.
• Format: Journal Article
• Language: English
• Published: Boston Springer US 01.10.2008; Springer
• Subjects: Applied sciences; Characterization and Evaluation of Materials; Chemical vapor deposition (including plasma-enhanced cvd, mocvd, etc.); Chemistry and Materials Science; Cross-disciplinary physics: materials science; rheology; Electronics; Electronics and Microelectronics; Exact sciences and technology; Instrumentation; Materials; Materials Science; Methods of deposition of films and coatings; film growth and epitaxy; Microelectronic fabrication (materials and surfaces technology); Optical and Electronic Materials; Physics; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Solid State Physics; Wafer bonding; hybrid integration; silicon-on-insulator; compound semiconductors; photonic integrated circuits; Interfacial layer; Plasma assisted processing; Crystal defect; Optimization; Indium phosphide; Thin film; Silicon on insulator technology; Microelectronic fabrication; Stress effects; Silicon; PECVD; Void; Diffusion; Bonding; Wafer; Gas absorption; Annealing; Oxide layer; Epitaxial film; X ray diffraction; Surface treatment; Plasma chemistry; High energy; Silicon oxides; Amorphous hydrogenated material; Integrated circuit; Covalent bond; Plasma deposition; Surface energy; III-V semiconductors
• ISSN: 0361-5235; 1543-186X
• DOI: 10.1007/s11664-008-0489-1

We report a low-temperature process for covalent bonding of thermal SiO 2 to plasma-enhanced chemical vapor deposited (PECVD) SiO 2 for Si-compound semiconductor integration. A record-thin interfacial oxide layer of 60 nm demonstrates sufficient capability for gas byproduct diffusion and absorption, leading to a high surface energy of 2.65 J/m 2 after a 2-h 300°C anneal. O 2 plasma treatment and surface chemistry optimization in dilute hydrofluoric (HF) solution and NH 4 OH vapor efficiently suppress the small-size interfacial void density down to 2 voids/cm 2 , dramatically increasing the wafer-bonded device yield. Bonding-induced strain, as determined by x-ray diffraction measurements, is negligible. The demonstration of a 50 mm InP epitaxial layer transferred to a silicon-on-insulator (SOI) substrate shows the promise of the method for wafer-scale applications.