A low-power high-performance configurable auto-gain control loop for a digital hearing aid SoC

A low-power, configurable auto-gain control loop for a digital hearing aid system on a chip （SoC） is presented. By adopting a mixed-signal feedback control structure and peak detection and judgment, it can work in automatic gain or variable gain control modes through a digital signal processing unit...

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Bibliographic Details
Published inJournal of semiconductors Vol. 34; no. 10; pp. 149 - 154
Main Author 陈铖颖 刘海南 黑勇 范军 胡晓宇
Format Journal Article
LanguageEnglish
Published 01.10.2013
Subjects
Circuits
Configurable
Digital
Direct reduction
Feedback control
Hearing
Noise levels
Semiconductors
SoC
低功耗
信号处理单元
助听器
可配置
性能
控制环路
自动增益
Online AccessGet full text
ISSN1674-4926
DOI10.1088/1674-4926/34/10/105011

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Summary:A low-power, configurable auto-gain control loop for a digital hearing aid system on a chip （SoC） is presented. By adopting a mixed-signal feedback control structure and peak detection and judgment, it can work in automatic gain or variable gain control modes through a digital signal processing unit. A noise-reduction and dynamic range （DR） improvement technique is also used to ensure the DR of the circuit in a low-voltage supply. The circuit is implemented in an SMIC 0.13 μm 1P8M CMOS process. The measurement results show that in a I V power supply, 1.6 kHz input frequency and 200 mVp-p, the SFDR is 74.3 dB, the THD is 66.1 dB, and the total power is 89 μW, meeting the application requirements of hearing aid SoCs.
Bibliography:Chen Chengying, Liu Hainan, Hei Yong, Fan Jun, Hu Xiaoyu（ Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China）
A low-power, configurable auto-gain control loop for a digital hearing aid system on a chip （SoC） is presented. By adopting a mixed-signal feedback control structure and peak detection and judgment, it can work in automatic gain or variable gain control modes through a digital signal processing unit. A noise-reduction and dynamic range （DR） improvement technique is also used to ensure the DR of the circuit in a low-voltage supply. The circuit is implemented in an SMIC 0.13 μm 1P8M CMOS process. The measurement results show that in a I V power supply, 1.6 kHz input frequency and 200 mVp-p, the SFDR is 74.3 dB, the THD is 66.1 dB, and the total power is 89 μW, meeting the application requirements of hearing aid SoCs.
hearing aid device; low power; gain control; digital feedback
11-5781/TN
ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 23
ISSN:1674-4926
DOI:10.1088/1674-4926/34/10/105011