Flash ADC-based digital LDO with non-linear decoder and exponential-ratio array

• Published in: Electronics letters Vol. 55; no. 10; pp. 585 - 587
• Main Authors: Ding, Zhendong, Xu, Xinyu, Song, Haixin, Rhee, Woogeun, Wang, Zhihua
• Format: Journal Article
• Language: English
• Published: The Institution of Engineering and Technology 16.05.2019
• Subjects: analogue‐digital conversion; Circuits and systems; CMOS integrated circuit; CMOS integrated circuits; current 0.04 mA to 82.7 mA; current 48.0 mA; exponential‐ratio array; flash ADC‐based digital LDO; flash ADC‐based parallel comparison; frequency 1.0 MHz; high load driving capacity; low‐dropout regulator; nonlinear decoder; power switch array; size 65 nm; time 6.0 mus; transient response; voltage 0.9 V; voltage 1.0 V; voltage regulators; high load driving capacity; size 65 nm; exponential-ratio array; transient response; low-dropout regulator; voltage 1.0 V; current 48.0 mA; time 6.0 mus; analogue-digital conversion; current 0.04 mA to 82.7 mA; frequency 1.0 MHz; voltage 0.9 V; flash ADC-based parallel comparison; voltage regulators; nonlinear decoder; power switch array; flash ADC-based digital LDO; CMOS integrated circuit; CMOS integrated circuits
• ISSN: 0013-5194; 1350-911X; 1350-911X
• DOI: 10.1049/el.2019.0505

This Letter presents a digital low-dropout regulator (LDO) that achieves fast transient response with a flash ADC-based parallel comparison. A non-linear decoder is employed in the flash ADC to further enhance the transient response. In the design of the power switch array, an exponential-ratio array (ERA) is adopted for high load driving capacity. The proposed digital LDO implemented in 65-nm CMOS achieves a load range of 0.04–82.7 mA when the input voltage and the output voltage are 1.0 and 0.9 V, respectively. The digital LDO achieves a settling time of 6 μs with a load step of 48 mA, exhibiting the state-of-the-art normalised settling time for the clock frequency of 1 MHz.