Low noise frequency synthesizer with self-calibrated voltage controlled oscillator and accurate AFC algorithm

A low noise phase locked loop （PLL） frequency synthesizer implemented in 65 nm CMOS technology is introduced. A VCO noise reduction method suited for short channel design is proposed to minimize PLL output phase noise. A self-calibrated voltage controlled oscillator is proposed in cooperation with t...

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Bibliographic Details
Published inJournal of semiconductors Vol. 35; no. 9; pp. 131 - 135
Main Author 秦鹏 李金波 康健 李小勇 周健军
Format Journal Article
LanguageEnglish
Published 01.09.2014
Subjects
AFC
Circuits
Frequency synthesizers
Low noise
Noise
Noise reduction
Semiconductors
Tuning
Voltage controlled oscillators
低噪声
压控振荡器
搜索算法
电压控制振荡器
相位噪声
自校准
频率合成器
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Summary:A low noise phase locked loop （PLL） frequency synthesizer implemented in 65 nm CMOS technology is introduced. A VCO noise reduction method suited for short channel design is proposed to minimize PLL output phase noise. A self-calibrated voltage controlled oscillator is proposed in cooperation with the automatic frequency calibration circuit, whose accurate binary search algorithm helps reduce the VCO tuning curve coverage, which reduces the VCO noise contribution at PLL output phase noise. A low noise, charge pump is also introduced to extend the tuning voltage range of the proposed VCO, which further reduces its phase noise contribution. The frequency synthesizer generates 9.75-11.5 GHz high frequency wide band local oscillator （LO） carriers. Tested 11.5 GHz LO bears a phase noise of-104 dBc/Hz at 1 MHz frequency offset. The total power dissipation of the proposed frequency synthesizer is 48 mW. The area of the proposed frequency synthesizer is 0.3 mm^2, including bias circuits and buffers.
Bibliography:Qin Peng, Li Jinbo, Kang Jian, Li Xiaoyong, Zhou Jianjun （Centre for Analog/Radio Frequency Integrated Circuits （CARFIC）, Shanghai Jiao Tong University, Shanghai 200240, China）
A low noise phase locked loop （PLL） frequency synthesizer implemented in 65 nm CMOS technology is introduced. A VCO noise reduction method suited for short channel design is proposed to minimize PLL output phase noise. A self-calibrated voltage controlled oscillator is proposed in cooperation with the automatic frequency calibration circuit, whose accurate binary search algorithm helps reduce the VCO tuning curve coverage, which reduces the VCO noise contribution at PLL output phase noise. A low noise, charge pump is also introduced to extend the tuning voltage range of the proposed VCO, which further reduces its phase noise contribution. The frequency synthesizer generates 9.75-11.5 GHz high frequency wide band local oscillator （LO） carriers. Tested 11.5 GHz LO bears a phase noise of-104 dBc/Hz at 1 MHz frequency offset. The total power dissipation of the proposed frequency synthesizer is 48 mW. The area of the proposed frequency synthesizer is 0.3 mm^2, including bias circuits and buffers.
11-5781/TN
65 nm CMOS; self-calibrated VCO; accurate AFC search algorithm; low noise frequency synthesizer;charge pump
ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 23
ISSN:1674-4926
DOI:10.1088/1674-4926/35/9/095007