朱樟明, 钟. (2016). A 0.1-1.5 GHz, low jitter, area efficient PLL in 55-nm CMOS process. Journal of semiconductors, 37(5), 90-96. https://doi.org/10.1088/1674-4926/37/5/055004
Chicago Style (17th ed.) Citation朱樟明, 钟波. "A 0.1-1.5 GHz, Low Jitter, Area Efficient PLL in 55-nm CMOS Process." Journal of Semiconductors 37, no. 5 (2016): 90-96. https://doi.org/10.1088/1674-4926/37/5/055004.
MLA (9th ed.) Citation朱樟明, 钟波. "A 0.1-1.5 GHz, Low Jitter, Area Efficient PLL in 55-nm CMOS Process." Journal of Semiconductors, vol. 37, no. 5, 2016, pp. 90-96, https://doi.org/10.1088/1674-4926/37/5/055004.
Warning: These citations may not always be 100% accurate.