A 0.1-1.5 GHz, low jitter, area efficient PLL in 55-nm CMOS process

A 0.1-1.5 GHz, 3.07 pS root mean squares （RMS）jitter, area efficient phase locked loop （PLL） with multiphase clock outputs is presented in this paper. The size of capacitor in the low pass filter （LPF） is significantly decreased by implementing a dual path charge pump （CP） technique in this PLL. Sub...

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Bibliographic Details
Published inJournal of semiconductors Vol. 37; no. 5; pp. 90 - 96
Main Author 钟波 朱樟明
Format Journal Article
LanguageEnglish
Published 01.05.2016
Subjects
Capacitors
Clocks
CMOS
CMOS工艺
Detectors
Jitter
Noise
Power consumption
Semiconductors
低抖动
低通滤波器
电压控制振荡器
相位噪声
纳米
锁相环技术
面积
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Summary:A 0.1-1.5 GHz, 3.07 pS root mean squares （RMS）jitter, area efficient phase locked loop （PLL） with multiphase clock outputs is presented in this paper. The size of capacitor in the low pass filter （LPF） is significantly decreased by implementing a dual path charge pump （CP） technique in this PLL. Subject to specified power con- sumption, a novel optimization method is introduced to optimize the transistor size in the voltage control oscillator （VCO）, CP and phase/frequency detector （PFD） in order to minimize clock jitter. This method could improve 3-6 dBc/Hz phase noise. The proposed PLL has been fabricated in 55 nm CMOS process with an integrated 16 pF metal-oxide-metal （MOM） capacitor, occupies 0.05 mm2 silicon area, the measured total power consumption is 2.8 mW @ 1.5 GHz and the phase noise is -102 dBc/Hz @ 1 MHz offset frequency.
Bibliography:phase lock loop; freqency synthesizer; dual path charge pump; CMOS
11-5781/TN
A 0.1-1.5 GHz, 3.07 pS root mean squares （RMS）jitter, area efficient phase locked loop （PLL） with multiphase clock outputs is presented in this paper. The size of capacitor in the low pass filter （LPF） is significantly decreased by implementing a dual path charge pump （CP） technique in this PLL. Subject to specified power con- sumption, a novel optimization method is introduced to optimize the transistor size in the voltage control oscillator （VCO）, CP and phase/frequency detector （PFD） in order to minimize clock jitter. This method could improve 3-6 dBc/Hz phase noise. The proposed PLL has been fabricated in 55 nm CMOS process with an integrated 16 pF metal-oxide-metal （MOM） capacitor, occupies 0.05 mm2 silicon area, the measured total power consumption is 2.8 mW @ 1.5 GHz and the phase noise is -102 dBc/Hz @ 1 MHz offset frequency.
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SourceType-Scholarly Journals-1
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content type line 23
ISSN:1674-4926
DOI:10.1088/1674-4926/37/5/055004