Optimized Submodule Capacitor Ripple Voltage Suppression of an MMC-Based Power Electronic Transformer

Modular multilevel converter (MMC)-based power electronic transformers (PETs) present a promising solution for connecting AC/DC microgrids to facilitate renewable energy access. However, the capacitor ripple voltage in MMC-based PET submodules hinders volume optimization and power density enhancemen...

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Published inElectronics (Basel) Vol. 14; no. 12; p. 2385
Main Authors Lai, Jinmu, Wu, Zijian, Jia, Xianyi, Wang, Yaoqiang, Liu, Yongxiang, Zhu, Xinbing
Format Journal Article
LanguageEnglish
Published Basel MDPI AG 11.06.2025
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Summary:Modular multilevel converter (MMC)-based power electronic transformers (PETs) present a promising solution for connecting AC/DC microgrids to facilitate renewable energy access. However, the capacitor ripple voltage in MMC-based PET submodules hinders volume optimization and power density enhancement, significantly limiting their application in distribution networks. To address this issue, this study introduces an optimized method for suppressing the submodule capacitor ripple voltage in MMC-based PET systems under normal and grid fault conditions. First, an MMC–PET topology featuring upper and lower arm coupling is proposed. Subsequently, a double-frequency circulating current injection strategy is incorporated on the MMC side to eliminate the double-frequency ripple voltage of the submodule capacitor. Furthermore, a phase-shifting control strategy is applied in the isolation stage of the dual-active bridge (DAB) to transfer the submodule capacitor selective ripple voltages to the isolation stage coupling link, effectively eliminating the fundamental frequency ripple voltage. The optimized approach successfully suppresses capacitor ripples without increasing current stress on the isolated-stage DAB switches, even under grid fault conditions, which are not addressed by existing ripple suppression methods, thereby reducing device size and cost while ensuring reliable operation. Specifically, the peak-to-peak submodule capacitor ripple voltage is reduced from 232 V to 10 V, and the peak current of the isolation-stage secondary-side switch is limited to ±90 A. The second harmonic ripple voltage on the LVDC bus can be decreased from ±5 V to ±1 V with the proposed method under the asymmetric grid voltage condition. Subsequently, a system simulation model is developed in MATLAB/Simulink. The simulation results validated the accuracy of the theoretical analysis and demonstrated the effectiveness of the proposed method.
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content type line 14
ISSN:2079-9292
2079-9292
DOI:10.3390/electronics14122385