Graph Analytics Accelerators for Cognitive Systems

Hardware accelerators are known to be performance and power efficient. This article focuses on accelerator design for graph analytics applications, which are commonly used kernels for cognitive systems. The authors propose a templatized architecture that is specifically optimized for vertex-centric...

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Bibliographic Details
Published inIEEE MICRO Vol. 37; no. 1; pp. 42 - 51
Main Authors Ozdal, Muhammet Mustafa, Yesil, Serif, Taemin Kim, Ayupov, Andrey, Greth, John, Burns, Steven, Ozturk, Ozcan
Format Journal Article
LanguageEnglish
Published Los Alamitos IEEE 01.01.2017
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Accelerators
Cognitive models
Computational modeling
Computer architecture
Computer graphics
Computer memory
Customization
Data structures
Design
Energy conversion efficiency
Graph analytics
Kernels
parallel architectures
Parallel processing
Random access memory
Scheduling
special-purpose and application-based systems
Synchronization
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Summary:Hardware accelerators are known to be performance and power efficient. This article focuses on accelerator design for graph analytics applications, which are commonly used kernels for cognitive systems. The authors propose a templatized architecture that is specifically optimized for vertex-centric graph applications with irregular memory access patterns, asynchronous execution, and asymmetric convergence. The proposed architecture addresses the limitations of existing CPU and GPU systems while providing a customizable template. The authors' experiments show that the generated accelerators can outperform a high-end CPU system with up to 3 times better performance and 65 times better power efficiency.
ISSN:0272-1732
1937-4143
DOI:10.1109/MM.2017.7