Optimization of a Cu CMP process modeling parameters of nanometer integrated circuits

A copper chemical mechanical polishing (Cu CMP) process is reviewed and analyzed from the view of chemical physics. Three steps Cu CMP process modeling is set up based on the actual process of manufacturing and pattern-density-step-height (PDSH) modeling from MIT. To catch the pattern dependency, a...

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Bibliographic Details
Published inJournal of semiconductors Vol. 33; no. 8; pp. 127 - 134
Main Author 阮文彪 陈岚 马天宇 方晶晶 张贺 叶甜春
Format Journal Article
LanguageEnglish
Published 01.08.2012
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ISSN1674-4926
DOI10.1088/1674-4926/33/8/086001

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Summary:A copper chemical mechanical polishing (Cu CMP) process is reviewed and analyzed from the view of chemical physics. Three steps Cu CMP process modeling is set up based on the actual process of manufacturing and pattern-density-step-height (PDSH) modeling from MIT. To catch the pattern dependency, a 65 nm testing chip is designed and processed in the foundry. Following the model parameter extraction procedure, the model parameters are extracted and verified by testing data from the 65 nm testing chip. A comparison of results between the model predictions and test data show that the former has the same trend as the latter and the largest deviation is less than 5 nm. Third party testing data gives further evidence to support the great performance of model parameter optimization. Since precise CMP process modeling is used for the design of manufacturability (DFM) checks, critical hotspots are displayed and eliminated, which will assure good yield and production capacity of IC.
Bibliography:Ruan Wenbiao, Chen Lan, Ma Tianyu, Fang Jingjing, Zhang He, and Ye Tianchun Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
11-5781/TN
chemical mechanical polishing; process modeling; parameter extraction; modeling verification;hotspot
A copper chemical mechanical polishing (Cu CMP) process is reviewed and analyzed from the view of chemical physics. Three steps Cu CMP process modeling is set up based on the actual process of manufacturing and pattern-density-step-height (PDSH) modeling from MIT. To catch the pattern dependency, a 65 nm testing chip is designed and processed in the foundry. Following the model parameter extraction procedure, the model parameters are extracted and verified by testing data from the 65 nm testing chip. A comparison of results between the model predictions and test data show that the former has the same trend as the latter and the largest deviation is less than 5 nm. Third party testing data gives further evidence to support the great performance of model parameter optimization. Since precise CMP process modeling is used for the design of manufacturability (DFM) checks, critical hotspots are displayed and eliminated, which will assure good yield and production capacity of IC.
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ISSN:1674-4926
DOI:10.1088/1674-4926/33/8/086001