Reducing process variation impact on replica-timed static random access memory sense timing

• Published in: Integration (Amsterdam) Vol. 42; no. 4; pp. 437 - 448
• Main Authors: Desai, Nishith N., Haigh, Jonathan R., Clark, Lawrence T.
• Format: Journal Article
• Language: English
• Published: Amsterdam Elsevier B.V 01.09.2009; Elsevier
• Subjects: Applied sciences; CMOS memory integrated circuits; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Integrated circuits; Integrated circuits by function (including memories and processors); Magnetic and optical mass memories; Memory architecture; Programmable timers; Replica timing; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; SRAM; Storage and reproduction of information; Programmable timers; Memory architecture; SRAM; Replica timing; CMOS memory integrated circuits; Memory devices; High performance; Static random access memory; Cache memory; Random access memory; CMOS memory circuits; Mismatching; Sense amplifier; Optimal design; Integrated circuit; Delay time; CMOS integrated circuits; Microprocessor
• ISSN: 0167-9260; 1872-7522
• DOI: 10.1016/j.vlsi.2009.03.002

The read access delay of a static random access memory (SRAM) is dominated by the time required to develop a voltage differential on the bit-lines, particularly for small, fast level-1 (L1) caches in microprocessors. For a robust design, the bit-lines must develop a differential sufficient to overcome mismatch due to sense amplifier offsets and other signal path components before the data is sensed. This must be accomplished across all process skews and voltages. This paper proposes a design and optimization technique to minimize the bit-line voltage differential variation across process corners and voltages, which increases the read frequency by reducing the delay guard-band required at the design process corner. The technique reduces the required timing guard-band by minimizing the effects of process variation on the circuit delays. On a 90 nm high-performance cache memory data array, the typical corner guard-band required to generate the differential is reduced by 78%. Total variation in bit-line differential is reduced from 243 to 45 mV across process and voltage corners.