DC and analog/RF performance of C-shaped pocket TFET (CSP-TFET) with fully overlapping gate

• Published in: Chinese physics B Vol. 31; no. 5; pp. 58501 - 814
• Main Authors: Chen, Zi-Xin, Liu, Wei-Jing, Liu, Jiang-Nan, Wang, Qiu-Hui, Zhang, Xu-Guo, Xu, Jie, Li, Qing-Hua, Bai, Wei, Tang, Xiao-Dong
• Format: Journal Article
• Language: English
• Published: Chinese Physical Society and IOP Publishing Ltd 01.04.2022; College of Electronics and Information Engineering,Shanghai University of Electric Power,Shanghai 200090,China%GTA Semiconductor Corporation Limited,Shanghai 200123,China%Key Laboratory of Polar Materials and Devices,East China Normal University,Shanghai 200041,China
• Subjects: double gate; pocket; tunnel field effect transistor; tunnel field effect transistor; double gate; pocket
• ISSN: 1674-1056; 2058-3834
• DOI: 10.1088/1674-1056/ac43a6

A C-shaped pocket tunnel field effect transistor (CSP-TFET) has been designed and optimized based on the traditional double-gate TFETs by introducing a C-shaped pocket region between the source and channel to improve the device performance. A gate-to-pocket overlapping structure is also examined in the proposed CSP-TFET to enhance the gate controllability. The effects of the pocket length, pocket doping concentration and gate-to-pocket overlapping structure on the DC and analog/RF characteristics of the CSP-TFET are estimated after calibrating the tunneling model in double-gate TFETs. The DC and analog/RF performance such as on-state current ( I on ), on/off current ratio ( I on / I off ), subthreshold swing ( SS ) transconductance ( g m ), cut-off frequency ( f T ) and gain–bandwidth product (GBP) are investigated. The optimized CSPTFET device exhibits excellent performance with high I on (9.98 × 10 −4 A/μm), high I on / I off (∼ 10 11 ), as well as low SS (∼ 12 mV/dec). The results reveal that the CSP-TFET device could be a potential alternative for the next generation of semiconductor devices.