Impact of material properties and device architecture on the device performance for a gate all around nanowire tunneling FET

• Published in: Materials research express Vol. 4; no. 11; pp. 114002 - 114008
• Main Authors: Singh, S K, Gupta, A, Yu, H W, Nagarajan, V, Anandan, D, Kakkerla, R K, Chang, E Y
• Format: Journal Article
• Language: English
• Published: IOP Publishing 01.11.2017
• Subjects: band-to-band tunneling (BTBT); interface trap charge (ITC); sub-threshold swing (SS); tunnel FET (TFET)

This paper systematically investigates the impact of gate dielectric, channel dimensional profile and the interface trap charge density on a homojunction indium-arsenide (InAs) gate all around nanowire tunneling FET (HJ-GAA-TFET). Device models were calibrated against the experimental data and simul...