Impact of material properties and device architecture on the device performance for a gate all around nanowire tunneling FET
This paper systematically investigates the impact of gate dielectric, channel dimensional profile and the interface trap charge density on a homojunction indium-arsenide (InAs) gate all around nanowire tunneling FET (HJ-GAA-TFET). Device models were calibrated against the experimental data and simul...
Saved in:
Published in | Materials research express Vol. 4; no. 11; pp. 114002 - 114008 |
---|---|
Main Authors | , , , , , , |
Format | Journal Article |
Language | English |
Published |
IOP Publishing
01.11.2017
|
Subjects | |
Online Access | Get full text |
Cover
Loading…
Be the first to leave a comment!