Impact of material properties and device architecture on the device performance for a gate all around nanowire tunneling FET
This paper systematically investigates the impact of gate dielectric, channel dimensional profile and the interface trap charge density on a homojunction indium-arsenide (InAs) gate all around nanowire tunneling FET (HJ-GAA-TFET). Device models were calibrated against the experimental data and simul...
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Published in | Materials research express Vol. 4; no. 11; pp. 114002 - 114008 |
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Main Authors | , , , , , , |
Format | Journal Article |
Language | English |
Published |
IOP Publishing
01.11.2017
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Subjects | |
Online Access | Get full text |
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Summary: | This paper systematically investigates the impact of gate dielectric, channel dimensional profile and the interface trap charge density on a homojunction indium-arsenide (InAs) gate all around nanowire tunneling FET (HJ-GAA-TFET). Device models were calibrated against the experimental data and simulations were performed to investigate the underlying physics. Device on-off (Ion/Ioff) ratio was considered as key figure-of-merit (FOM) to improve. It is observed that the off current (Ioff) is a weak function of dielectric constant, however, the on current (Ion) increases from 1.51 × 10−7 A µm−1 to 1.79 × 10−6 A µm−1 as the dielectric constant increases from SiO2 to La2O3. It was also observed that as the diameter increases, both Ion and Ioff increases. Ion/Ioff ratio is independent for higher channel lengths but as the channel length is reduced below 30 nm, Ioff increases causing degradation in Ion/Ioff ratio. Finally, the effect of interface traps was realised on the Ion/Ioff ratio. Interface traps impact the flat-band voltage causing a shift in the device performance. It is observed that as the trap density increases, Ioff degrades rapidly by ~3 orders in magnitude. |
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Bibliography: | MRX-105307.R1 |
ISSN: | 2053-1591 2053-1591 |
DOI: | 10.1088/2053-1591/aa95f9 |